Electrical performance of an interconnect structure, such as one including a filled through hole with conductive material in an IC substrate, may be adversely affected by undesired electrical resistivity of the interconnect structure resulting from deficiencies in manufacturing such an interconnect structure. For example, a laser drilled through hole may potentially have high wall roughness, asymmetrical shape with dimensional variations, and misalignments at the top and bottom diameter of the through hole. A combination of these factors may result in voids when filling the through hole with a conductive material (e.g., by plating copper) to form an interconnect structure. The formation of voids may lead to reduced current carrying capability of the interconnect structure. Using a single current density during the filling process may increase the probability of voids forming and may potentially lead to long plating times and large recesses in the filled interconnect.